Coding is often used to reduce communication errors by deliberately introducing redundancy into a transmitted signal. When the signal is received, the redundancy introduced by the code can be used to detect and/or reduce errors. For example, a simple parity check code is obtained by transmitting blocks of N+1 bits, where N bits are data bits and one bit is a parity bit selected to make the parity of each N+1 bit block even. Such a code can provide detection, but not correction, of single bit errors. Introduction of more than one parity bit can improve code error reduction performance (e.g. by providing detection and/or correction of multiple bit errors). This code is an example of a block parity check code.
Block parity check codes can be considered more systematically in terms of a parity check matrix H. The matrix H has R rows and C columns, where C>R. Transmitted code words x are in the null space of H (i.e., Hx=0). Thus the columns of H correspond to symbols in the code word x (typically binary bits), and each row of H corresponds to a parity check condition on the code word x. Since a transmitted code word has C bits subject to R linear conditions, the data content of a code word is C−R bits if the rows of H are linearly independent. In some cases, the rows of H are not linearly independent, and in these cases the data content of a block is C−R*, where R* is the number of linearly independent rows of H (i.e., the dimension of the row space of H). When the rows of H are not linearly independent, H is transformed to an equivalent matrix Henc having linearly independent rows for encoding. However, the original H matrix is still used for decoding. The rate of a block code is the ratio (C−R*)/C, and is a measure of the amount of redundancy introduced by the code. For example, a rate ½ code has one parity bit for each data bit in a block, and a rate ¾ code has one parity bit for each three data bits in a block.
A parity check code is completely defined by its parity check matrix H. Accordingly, encoding can be regarded as the process of mapping a sequence of data bits to code words in the null space of H. This encoding is typically done by constructing a generator matrix G from H such that a message vector u is mapped into a code word x in the null space of H via xT=uTG. Methods for constructing G given H are known in the art. For example, if H has the form [A|I] where A has dimensions n−k by k and I is an n−k dimensional identity matrix, G has the form [I|−A]. If H does not have this special form, G can still be constructed, but will not have the form [I|−A]. Similarly, decoding can be regarded as the process of estimating which code word was transmitted, given a received code word x′ which need not be in the null space of H due to transmission errors. Various methods for efficiently performing these encoding and decoding operations in practice have been developed over time.
In the course of this development, low density parity check (LDPC) codes have emerged as an especially interesting class of codes. The defining characteristic of an LDPC code is that the parity check matrix H is sparse (i.e., is mostly zeros). It is customary to use the notation LDPC(B, D) to refer to an LDPC code, where B is the total number of bits in a block, and D is the number of data bits in a block. Thus such a code has a parity check matrix H having B columns and B-D rows, if the rows are linearly independent. Some LDPC codes are referred to as “regular” codes because they have the same number dc of non-zero elements in every row of H and have the same number dv of non-zero elements in every column of H. Such codes are often referred to as (dv, dc) LDPC codes. For example, a (3, 6) LDPC code has dv=3 and dc=6. In some cases, further structure has been imposed on H in order to improve encoding and/or decoding efficiency. For example, it is generally preferred for no two rows (or columns) of the H matrix to have more than one “1” in common.
The structure of regular LDPC codes can be appreciated more clearly in connection with a graph, as shown on FIG. 1. In the representation of FIG. 1, a set of variable nodes 110 and a set of check nodes 120 are defined. Each variable node is connected to dv check nodes, and each check node is connected to dc variable nodes. In the example of FIG. 1, dc=3, dc=6, and the connections from variable nodes to check nodes are not completely shown to preserve clarity. There is one variable node for each bit in a code word (i.e., there are C variable nodes), and there is one check node for each parity check condition defined by H (i.e., there are R check nodes). It is useful to define N(m) as the set of variable nodes connected to check node m, and M(n) as the set of check nodes connected to variable node n.
LDPC decoding can be regarded as a process of estimating values for the variable nodes given received variable data (which may have errors) subject to parity check conditions defined by each check node. Two approaches to decoding have been extensively considered: hard decision decoding and soft decision decoding. In hard decision decoding, received variable data is quantized to either of two binary values, and then error checking defined by the check nodes is performed on the quantized values. In the context of LDPC decoding, this approach includes “bit-flipping” decoding methods and majority-logic decoding methods. Suppose that a received code word has only a single bit error at variable node k. In this case, the check node conditions will be satisfied at all check nodes except for check nodes M(k). Since variable node k is the common element to all check nodes showing a violation, it should be flipped. While variations of such bit-flipping methods have been developed, a common feature of these approaches is quantization of received bit data to binary levels, followed by error correction processing.
As might be expected, such quantization of received bit data incurs a performance penalty, because information is lost. For example, if an analog signal between 0 and 1 is quantized to binary values of 0 and 1, received values of 0.51 and 0.99 are both quantized to 1. Clearly the “1” resulting from quantization of 0.51 is significantly less certain than the “1” resulting from quantization of 0.99. This performance penalty can be avoided by soft decision decoding. For LDPC codes, soft decision decoding is typically implemented as a message passing belief propagation (BP) algorithm. In such algorithms, variable messages are calculated in the variable nodes and passed to the check nodes. Next, check messages are computed in the check nodes and passed to the variable nodes. In both steps, computation of outgoing messages depends on received message inputs. These steps are repeated until a convergence condition is met (or a maximum number of iterations is reached). Soft decision decoding with a BP algorithm typically provides good performance, but such approaches tend to be more resource-intensive than hard decision approaches. Equivalently, soft decision decoding typically cannot be performed as rapidly as hard decision decoding.
This trade-off has motivated development of hybrid approaches having aspects of both hard and soft decision decoding to provide improved performance with reduced complexity. For example, weighted bit flipping (WBF) and modified WBF methods are described by Zhang and Fossorier in IEEE Comm. Lett., v8 n3, pp. 165-167, 2004. In these methods, bits are flipped responsive to calculations performed on unquantized received bits. These bit-flipping methods (as well as simple bit-flipping) typically require a search to be performed over all variable nodes. For example, in simple bit-flipping let ERR(n) be the number of parity check violations in the set of check nodes M(n) associated with variable node n. Bits corresponding to variable nodes having a maximal (or above-threshold) value of ERR(n) are flipped. In this example, a search is required to identify these variable nodes. Such a search can undesirably increase the computational resources required for decoding.
Hybrid decoding of LDPC codes is also considered in US patent application 2004/0148561, where various hybrid methods including both a bit flipping step and a belief propagation step are considered. Approaches of this kind do not provide simple implementation, since both bit-flipping and belief propagation are performed. In particular, these approaches do not alleviate the above-noted disadvantage of reduced decoding speed exhibited by conventional BP decoding.
Accordingly, it would be an advance in the art to provide hybrid decoding of LDPC codes that overcomes these disadvantages. More specifically, it would be an advance to provide a hybrid decoding method that does not require searching nodes for maximal (or above threshold) values and does not require implementation of conventional belief propagation.